This is an improvement of the invention shown in U.S. Pat. No. 5,717,243, the entire disclosure of which is herein incorporated by reference. Integrated circuits have one or more levels of metal formed on dielectric material that covers a semiconductor substrate. The levels of metal are separated by dielectric material. The substrate that holds the integrated circuits is made of semiconductor material. The metal levels are patterned into lines that can be characterized as either signal lines (which carry a signal), return lines (which are signal lines carrying current in the opposite direction to another signal line), or lines attached to ground (ground lines). Parasitic currents can flow in the substrate due either to capacitive coupling or to inductive coupling to these metal lines.
Consider FIGS. 1(a) and 1(b) where one or more first metal line(s) 104 carries a signal and one or more ground lines 108 that run parallel to signal line(s) 104. The lines 104, 108 are supported on dielectric layer 16 that covers the semiconductor substrate 14. The substrate 14 is doped at around 10 to 20 ohm-cm. With this resistivity, the primary power loss is due to resistive current flow through the substrate that is capacitively generated from the signal line. The resistive current flow in the substrate caused by the signal line can be redirected by the presence of a nearby ground line which then tends to become the primary destination of this current. Without doing anything special, this will reduce the resistance somewhat but will not greatly reduce the resistive losses. This particular loss factor can be nearly eliminated by pursuing one of two strategies: The first strategy is to make the path so highly resistive that current cannot flow at all. The second strategy, pursued here, is to make the path so conductive that the resistive loss is very small even though the current is free to flow. The problem introduced by making the path conductive is that another parasitic current is formed. In many instances, this other parasitic current is worse than the eliminated parasitic current. This other parasitic current is an inductively induced image current L of the signal line in the conductive part of the substrate. This image current L is opposite to the current in the signal line and parallel in direction. The path of the capacitively generated current in the substrate from the signal line to the ground line is perpendicular to the signal line as shown by arrow C; the inductively induced current in the substrate is parallel to the signal line as shown by arrow L.
The substrate resistive loss due to inductive coupling to a heavily doped layer can be calculated. In this calculation, the substrate is doped with a buried layer with a resistance of 8.1 Ohms/square. The signal line 104 is above the dopant 20(a), as shown in FIG. 2(a), and is 2.5 um thick, 20 um wide, and 1,000 um long. The power loss in the substrate, P.sub.s, is EQU P.sub.s =V.sub.s.sup.2 /R.sub.s Equation (1)
where R.sub.s is the resistance in the conductive path through the substrate and V.sub.s is the voltage difference in the substrate below the metal line caused by mutual inductive coupling from the signal line above.
V.sub.s is related to the current in the metal line (I.sub.m) by the formula EQU V.sub.s =M.omega.I.sub.m Equation (2)
where M is the mutual inductance between the signal line 104 and the conductive path in the substrate 14, and .omega. is the frequency in radians/second. Substituting this into the formula for P.sub.s gives EQU P.sub.s =(M.omega.I.sub.m).sup.2 /R.sub.s Equation (3)
The active doped region of the substrate is assumed to be 30 .mu.ms wide and 1000 .mu.ms long. From analytic inductance equations, M=8.2 e -10 Henrys. R.sub.s, the resistance in the substrate below the signal line, is calculated from the sheet resistance and the geometry as EQU R.sub.s= (8.1 Ohms)(1000 .mu.m)/(30 .mu.m)=270 Ohms Equation (4)
Choosing a frequency of 5 GHz and substituting these values into Equation (3), we get EQU P.sub.s =2.50I.sub.m.sup.2 Equation (5)
where mks units are assumed. For comparison, the resistive loss in the metal is EQU P.sub.m =R.sub.m I.sub.m.sup.2= 0.75I.sub.m.sup.2 Equation (6)
The above analysis shows that in the prior art structure the resistive loss through the substrate is roughly comparable to but greater than the loss in the signal line 104 (in this case, more that 3 times greater). It would be desirable to reduce such losses.